FAULT-TOLERANT SELT-TIMED CIRCUITS

Abstract

The article considers the problem of developing synchronous and self-timed (ST) circuits that are tolerant to faults. Redundant ST coding and two-phase discipline ensures that ST circuits are more tolerant to the faults than synchronous counterparts. Duplicating ST channels instead of tripling reduces redundancy of the fault-tolerant ST circuits and retains their reliability level compared to synchronous counterparts