Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching

Cheng-Tsung Chang; Pin-Wei Chen; Wen‐Long Chin; Shih‐Hsiang Chou; Yu-Hua Yang

doi:10.1016/j.vlsi.2023.05.005

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Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching

Cheng-Tsung Chang Pin-Wei Chen Wen‐Long Chin Shih‐Hsiang Chou Yu-Hua Yang

Year: 2023 Journal: Integration Vol: 92 Pages: 99-105 Publisher: Elsevier BV

DOI: 10.1016/j.vlsi.2023.05.005

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Keywords:

Computer science Application-specific integrated circuit Computational complexity theory Redundancy (engineering) Throughput Matching (statistics) Parallel computing Critical path method Algorithm Reduction (mathematics) Field-programmable gate array Computer engineering Computer hardware Mathematics Engineering

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Advanced Vision and Imaging

Physical Sciences → Computer Science → Computer Vision and Pattern Recognition

Video Coding and Compression Technologies

Physical Sciences → Computer Science → Signal Processing

Advanced Image Processing Techniques

Physical Sciences → Computer Science → Computer Vision and Pattern Recognition

Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching

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