Low-Resource Hardware Architecture for Semi-Global Stereo Matching

Abstract

The semi-global matching algorithm is usually used for generating high-quality and real-time disparity maps in stereo vision systems. To reduce the hardware-resource consumption, we present a multi-stage pipeline hardware architecture with timesharing reuse for semi-global stereo matching. Combined with image down-sampling, jumping disparity, and a post processing, the presented architecture is used in a practical advanced driver-assistance system (ADAS), which is implemented on a Zynq-7 FPGA chip. The whole stereo matching architecture consumes 19,603 LUTs and 61.5 BRAM (36 KB), and the throughput is 2857 Million Disparity Estimation per second (MDE/S), which corresponds to a throughput of 31 fps when processing images with 1280∗960 resolution and 75 disparity levels.