Variation-Aware Analog Circuit Sizing in Carbon Nanotube

Abstract

Although deemed as one of the promising candidates to substitute CMOS transistors in the sub-10 nm regime, fabrication of Carbon Nanotube Field-Effect Transistors (CNFET) is still experiencing significant process variations. In this paper, we consider carbon nanotube diameter process variation in CNFET analog circuit sizing design. We systematically study a robust sizing methodology for designing analog CNFET circuits. We propose a multi-objective deterministic sizing flow to approach the best performance of analog CNFET circuits even under device parameter process variation. We use a design centering approach to obtain the optimal value of design parameters to ensure a robust circuit. Moreover, we have developed a generic multi-objective deterministic sizing optimization methodology using SPICE simulation for circuit performance verification by combining generalized boundary curves and normal boundary intersection schemes. The experimental results demonstrate that our proposed method can better approach the Pareto front than another common stochastic multi-objective optimizer.