Hardware Architecture of Stochastic Computing Neural Network

Abstract

Stochastic computing is a kind of logic calculation that converts binary into probabilistic coded digital pulse stream. At the cost of computing power and time delay, it has the computing advantages of low power consumption and high energy efficiency. In this paper, the basic concept of stochastic computing is explained, and a stochastic computing circuit with single-channel or multi-channel is designed to improve the speed and accuracy. Based on the stochastic computing circuit, the stochastic pulse neuron is designed, and the reconfigurable computing architecture of neural network, BUAA-ChouSuan, is realized. The design is implemented with KINTEX-7 (FPGA), the logic resource (lookup table, LUT) of stochastic MAC (multiply accumulate) is 80% lower than that of traditional MAC. In SCNN (stochastic convolutional neural network) experiment, LeNet and AlexNet are tested. Under the condition of 350 MHz clock frequency, the average energy efficiency can reach 0.536 TSOPS/W, and the utilization rate of processing unit (PE) can reach more than 90%.