Hardware Tripartite Synapse Architecture based on Stochastic Computing

Abstract

Research showed that the tripartite synapse has the capability of self-repairing in the spiking neural networks (SNNs), where the interactions between astrocyte, neuron and synapse underpin this mechanism. It has been used for the hardware electronic systems to enhance the fault-tolerant abilities, especially for the critical task applications. Due to the complex models of the tripartite synapse, its efficient hardware architecture and scalability are the research challenges. In this paper, an efficient hardware tripartite synapse architecture is proposed which is based on the Stochastic Computing (SC) technique. The SC is used to replace the conventional computing components such as DSPs in the hardware devices, and the extended stochastic logics are used to scale the data range during the calculation process. Results show that the proposed hardware architecture has the same output behaviours as the software simulations and has a low hardware resource consumption (with a reduction rate of >85% compared to state-of-the-art approach) which can maintain the system scalability for large SNNs.