JOURNAL ARTICLE

2P1-N3 Implementation of High-Performance Stereo Vision VLSI Processor

竹内 俊樹張山 昌論亀山 充隆

Year: 2001 Journal:   The Proceedings of JSME annual Conference on Robotics and Mechatronics (Robomec) Vol: 2001 (0)Pages: 65-65   Publisher: Japan Society Mechanical Engineers

Abstract

Standing up motion control of

Keywords:
Very-large-scale integration Computer science Stereopsis Artificial intelligence Computer vision Parallel computing Arithmetic Computer graphics (images) Embedded system Mathematics

Metrics

0
Cited By
0.00
FWCI (Field Weighted Citation Impact)
0
Refs
0.52
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Topics

Advanced Vision and Imaging
Physical Sciences →  Computer Science →  Computer Vision and Pattern Recognition
CCD and CMOS Imaging Sensors
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Image and Video Stabilization
Physical Sciences →  Computer Science →  Computer Vision and Pattern Recognition

Related Documents

JOURNAL ARTICLE

Architecture of a high-performance stereo vision VLSI processor

Masanori HariyamaSeung Hwan LeeMichitaka Kameyama

Journal:   Advanced Robotics Year: 2000 Vol: 14 (5)Pages: 329-332
JOURNAL ARTICLE

High-Performance VLSI Architecture for Stereo Vision

Young-Ho SeoDong-Wook Kim

Journal:   Journal of Broadcast Engineering Year: 2013 Vol: 18 (5)Pages: 669-679
JOURNAL ARTICLE

PIPE: a high performance VLSI processor implementation

Gary CraigJames GoodmanRandy H. KatzAndrew R. PleszkunKishore RamachandranJ. SayahJ. E. Smith

Journal:   Microprocessors and Microsystems Year: 1987 Vol: 11 (8)Pages: 451-451
JOURNAL ARTICLE

Stereo vision VLSI processor based on a recursive computation algorithm

K. MiuraMasanori HariyamaMichitaka Kameyama

Journal:   Society of Instrument and Control Engineers of Japan Year: 2003 Vol: 2 Pages: 1564-1567
JOURNAL ARTICLE

High performance VLSI processor architectures

Katz

Year: 1989 Pages: 5-8
© 2026 ScienceGate Book Chapters — All rights reserved.