A SystemC Virtual Prototyping based methodology for multi-standard SoC functional verification

Abstract

This paper describes a functional verification methodology for multi-standard wireless Systems-on-Chip (SoC) based on SystemC Virtual Prototyping (VP). The proposed semi-automatic pin-accurate RF VP generation method reduces huge handcrafting work to abstract circuitry into the event-driven simulation domain with satisfactory accuracy, while enabling the flexibility to choose different abstraction levels. A seamless transition between various signal abstractions is enabled by operator overload, e.g. passband and equivalent baseband in order to minimize simulation time according to test cases. This methodology is demonstrated for a low power RF transceiver with the achieved simulation speed of 500µs in 10s computation time.