A mixed-level virtual prototyping environment for SystemC-based design methodology

Sang‐Gyu Park; Sang-Yong Yoon; Soo‐Ik Chae

doi:10.1016/j.mejo.2008.05.010

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A mixed-level virtual prototyping environment for SystemC-based design methodology

Sang‐Gyu Park Sang-Yong Yoon Soo‐Ik Chae

Year: 2008 Journal: Microelectronics Journal Vol: 40 (7)Pages: 1082-1093 Publisher: Elsevier BV

DOI: 10.1016/j.mejo.2008.05.010

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Keywords:

SystemC Transaction-level modeling Computer science Virtual prototyping Software Embedded system Electronic system-level design and verification Computer architecture Abstraction Software prototyping Rapid prototyping High-level synthesis Operating system Software development Simulation Field-programmable gate array Engineering

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Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

VLSI and Analog Circuit Testing

Physical Sciences → Computer Science → Hardware and Architecture

Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

A mixed-level virtual prototyping environment for SystemC-based design methodology

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