Automatic generation of virtual prototypes

Abstract

Virtual prototyping as an embedded system design technique has the potential to significantly increase efficiency of the design process. An environment for automatic generation of virtual prototypes (VPs) directly from algorithmic-level descriptions is presented here. It is implemented as part of a unified design methodology and produces VSIA compliant VPs. When applied to an industrial design flow of a UMTS receiver, this environment for automatic generation of VPs produced significant speedups over traditional manual VP creation, with savings in the order of hundreds to thousands of person-hours.