Towards SAT-Based SBST Generation for RISC-V Cores

Abstract

The increasing amount and diversity of System-On-a-Chip (SoC) devices with short development times pose numerous challenges. The RISC-V initiative targets this market with a free and open ISA that supports custom instruction set extensions and accelerators to adapt to application specific scenarios and meet varying constraints w.r.t. efficiency, security, safety and computational power. In this context we target an appropriate test strategy to find manufacturing defects during production, and moreover, to detect degradation in the field. An essential part of this strategy will be so-called Software-Based Self-Tests (SBST). Manually developing SBST programs is a tedious and time-consuming task that requires the expertise of a skilled engineer with detailed knowledge about the specific architecture of the processor at hand. In contrast we present a staggered SBST approach for the automatic creation of SBST programs for RISC-V architectures with the help of SAT-based test pattern generation. First experimental results to demonstrate the feasibility of our approach are provided by test generation results for two exemplary RISC-V processor, each in two variants.