A Reconfigurable Convolution-in-Pixel CMOS Image Sensor Architecture

Abstract

The separation of the data capture and analysis in modern vision systems has\nled to a massive amount of data transfer between the end devices and cloud\ncomputers, resulting in long latency, slow response, and high power\nconsumption. Efficient hardware architectures are under focused development to\nenable Artificial Intelligence (AI) at the resource-limited end sensing\ndevices. One of the most promising solutions is to enable Processing-in-Pixel\n(PIP) scheme. However, the conventional schemes suffer from the low fill-factor\nissue. This paper proposes a PIP based CMOS sensor architecture, which allows\nconvolution operation before the column readout circuit to significantly\nimprove the image reading speed with much lower power consumption. The\nsimulation results show that the proposed architecture could support the\ncomputing efficiency up to 11.65 TOPS/W at the 8-bit weight configuration,\nwhich is three times as high as the conventional schemes. The transistors\nrequired for each pixel are only 2.5T, significantly improving the fill-factor.\n