Advanced 1.1um pixel CMOS image sensor with 3D stacked architecture

Abstract

This paper demonstrates an advanced 1.1um pixel backside illuminated CMOS image sensor with a 3D stacked architecture. The carrier wafer in conventional BSI is replaced by ASIC wafer, which contains a part of periphery circuit and is connected to the sensor wafer through bonding technology. With proper layout design and process improvement, the impact of 3D connection (Through Via, TV) on the sensor performance can be significantly minimized. In addition, for the first time, the degradation of stacked pixel performance during the folded circuit operation under sensor array is found and improved. The final stacked sensor exhibits the comparable pixel performances to conventional BSI. Furthermore, stacked architecture provides the opportunity to enhance sensor performance by the separate process tuning for sensor wafers (without any effect on ASIC wafers), leading to a further improvement of dark performance.