Optimizing Accelerator on FPGA for Deep Convolutional Neural Networks

Yong Dong; Wei Hu; Yonghao Wang; Qiang Jiao; Shuang Chen

doi:10.1007/978-3-030-60239-0_7

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Optimizing Accelerator on FPGA for Deep Convolutional Neural Networks

Yong Dong Wei Hu Yonghao Wang Qiang Jiao Shuang Chen

Year: 2020 Lecture notes in computer science Pages: 97-110 Publisher: Springer Science+Business Media

DOI: 10.1007/978-3-030-60239-0_7

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Keywords:

Computer science Convolutional neural network Bottleneck Field-programmable gate array Pipeline (software) Hardware acceleration Computer architecture Process (computing) Deep learning Efficient energy use Acceleration Computer engineering Set (abstract data type) Artificial intelligence Embedded system Parallel computing Operating system

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Advanced Neural Network Applications

Physical Sciences → Computer Science → Computer Vision and Pattern Recognition

CCD and CMOS Imaging Sensors

Physical Sciences → Engineering → Electrical and Electronic Engineering

Advanced Memory and Neural Computing

Physical Sciences → Engineering → Electrical and Electronic Engineering

Optimizing Accelerator on FPGA for Deep Convolutional Neural Networks

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