A RISC-V ISA Compatible Processor IP

Abstract

A processor is the core component of an electronic system. In this work, we present a high-performance general-purpose processor system, based on open source RISC-V instruction set architecture. Our processor has a 32-bit 5-stage pipeline core with separate 8 KB I-Cache and D-Cache, and supports virtual memory system. The processor supports integer, atomic and floating-point (single and double precision) instruction subset of RISC-V ISA. The nested vectored interrupt unit and the dedicated floating-point execution unit is included in the system to improve its real-time performance. To improve the execution speed of the processor, a branch prediction unit and a hardware Economic Value Added replacement policy for I-Cache and D-Cache is implemented. The performance of processor is evaluated using CoreMark and has a CoreMark value of 3.32 CoreMark/MHz. The design is implemented on Xilinx's Virtex-7 (XC7VX485tffg1761-2) FPGA and has maximum clock frequency of 60MHz.