A RISC-V ISA compatible processor IP for SoC

Abstract

The emergence of System-on-Chip technology has brought in opportunities in the form of reduced cycle time, superior performance and time-to-market considerations. Our work focusses on a new processor for a System on Chip. The system has a 32-bit, 5-stage pipelined processor, memory subsystem with virtual memory support, interrupt controller, memory error control module, and UART. The processor is based on RISC-V ISA. It supports Integer, Multiply, and Atomic instructions. Memory subsystem includes split caches and translation lookaside buffers. Interrupt controller supports four levels of preemptive priority and preemption can be programmed for individual interrupts. Memory error control module provides single error correction and double error detection for main memory. Wishbone B.3 bus standard is adopted as on-chip bus protocol. The design is implemented on Virtex-7 (XC7VX485tffg1761-2) board and achieves a peak clock frequency of 100MHz.