Low‐Power Computing: Vertical‐Tunneling Field‐Effect Transistor Based on WSe<sub>2</sub>‐MoS<sub>2</sub> Heterostructure with Ion Gel Dielectric (Adv. Electron. Mater. 7/2020)

Hyun Bae Jeon; Gwang Hyuk Shin; Khang June Lee; Sung‐Yool Choi

doi:10.1002/aelm.202070030

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Low‐Power Computing: Vertical‐Tunneling Field‐Effect Transistor Based on WSe₂‐MoS₂ Heterostructure with Ion Gel Dielectric (Adv. Electron. Mater. 7/2020)

Hyun Bae Jeon Gwang Hyuk Shin Khang June Lee Sung‐Yool Choi

Year: 2020 Journal: Advanced Electronic Materials Vol: 6 (7) Publisher: Wiley

DOI: 10.1002/aelm.202070030

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Keywords:

Materials science Quantum tunnelling Heterojunction Optoelectronics Dielectric Gate dielectric Transistor Field-effect transistor van der Waals force Ion Electrical engineering Voltage Physics Engineering Quantum mechanics

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2D Materials and Applications

Physical Sciences → Materials Science → Materials Chemistry

Low‐Power Computing: Vertical‐Tunneling Field‐Effect Transistor Based on WSe₂‐MoS₂ Heterostructure with Ion Gel Dielectric (Adv. Electron. Mater. 7/2020)

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