FPGA Based Human Detection Using Background Subtraction

Abstract

Detection of Human is a vital and difficult task in computer vision applications like police investigation, vehicle tracking and human following. Human detection in video stream is very important in public security management. In such security related cases detecting of object in video sequences is very important to understand the behavior of moving object normally background subtraction is used. In this paper we proposed a new hardware implementation of human detection based on background subtraction technique. The proposed architecture is coded using standard VHDL language and performance is checked in Spartan-6 FPGA board. The comparison result shows that the proposed architecture is better than existing in both hardware and image quality than existing techniques.