An Efficient FPGA based Background Subtraction Algorithm for Object Detection

Abstract

Object Detection is an integral part of security system where tracking accuracy and time plays a vital role. This makes moving object detection becomes one of the challenging tasks in current world scenario like video surveillance, traffic monitoring etc. In this paper, an efficient FPGA based Background Subtraction Algorithm for Object Detection is proposed. The process involves three stages of Pre-processing using median filter, Detection with background subtraction and Post-processing using Threshold technique. To achieve the optimum results of the total module, optimization is done at the architecture level of each block without affecting the accuracy of the processed data. The entire architecture is designed using VHDL language and implemented on Virtex-5 FPGA board. The comparison results prove that the proposed technique is more efficient than existing in terms of both hardware utilization and detection accuracy.