Automatic generation of application-specific FPGA overlays

Abstract

This work proposes a generic flow for designing application-specific FPGA overlays that can achieve bare metal performance while improving productivity, resulting in increased adoption of FPGAs by software developers. The proposed approach relies on automatic extraction of kernels in high-level language applications. Extracted Kernels are then systematically translated into optimized hardware circuits using RapidWright, which allows bypassing HDL design flows. Initial results show up to 19x productivity improvement over regular overlays, and higher Fmax compared to bare metal in several cases.