8.2: Invited Paper: Elevated‐Metal Metal‐Oxide Thin‐Film Transistor with Self‐Aligned Source/Drain Regions

Abstract

Driving of a large‐area, high‐resolution and high frame‐rate active‐matrix display demands proper control of the signal delay along a scan line, thus also the parasitic overlap capacitance between the source/drain (S/D) regions and the gate electrode of an address‐transistor. While such capacitance can be minimized by employing a transistor with the edges of the regions self‐aligned to those of the electrode, actual implementation is easier with a top‐gate rather than the more popularly deployed bottom‐gate architecture. Presently reported is the demonstration of a self‐aligned bottom‐gate indium‐gallium‐zinc oxide transistor. The extent of the overlap between the S/D and the bottom gate is determined by a thermal “activation” process, similar to how it is controlled in a conventional top‐gate, self‐aligned transistor.