High Speed Most Significant Bit First Truncated Multiplier

Abstract

This paper proposes a high-speed MSB first multiplier which works efficiently when successive inputs show gradual change which is usually the case for analog signals sampled at a high rate. When the speed of execution of various processes in digital signal processing units is considered, the easiest way to improve it is to use efficient and fast multiplier units. The proposed multiplier computes only one or two partial products when the successive inputs are similar as compared to eleven partial products in the conventional multiplier. The output truncation length can be controlled depending upon the application. The no. of clock cycles needed for multiplication in a conventional MSB first multiplier and the proposed highspeed multiplier are compared through FPGA Implementation. An average decrease of 14.7% in no. of clock cycles is observed when simulations are done for 1400 ECG ambulatory recordings from MIT BIH Arhythmia Database.