Design of most-significant-bit-first serial multiplier

LU LU; J.G. Kenney

doi:10.1049/el:19950824

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Design of most-significant-bit-first serial multiplier

LU LU J.G. Kenney

Year: 1995 Journal: Electronics Letters Vol: 31 (14)Pages: 1133-1135 Publisher: Institution of Engineering and Technology

DOI: 10.1049/el:19950824

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Abstract

The design of a two's complement most-significant-bit-first add and shift serial multiplier is presented. In this multiplier, one of the multiplicands is represented in full length, whereas the second multiplicand is presented in a bit-serial fashion with the most significant bit (MSB) first.

Keywords:

Multiplier (economics) Arithmetic Bit (key) 4-bit Computer science Computer hardware Mathematics Electronic engineering Engineering CMOS

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Analog and Mixed-Signal Circuit Design

Physical Sciences → Engineering → Biomedical Engineering

Quantum-Dot Cellular Automata

Physical Sciences → Computer Science → Computational Theory and Mathematics

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Design of most-significant-bit-first serial multiplier

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