FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training

Abstract

Deep Convolutional Neural Network (DCNN) is a class of machine learning algorithms that has wide application in pattern recognition, image recognition and video analysis. Convolutional layers in the network extract various features from a set of inputs and adapt parameters, before they do the classification. Training of DCNN is computationally intensive and has large memory requirement, but offers multiple degrees of parallelism, as similar structures are needed for computation at various intermediate stages. Training using a general purpose processing unit does not utilize parallelism of the network, and hence, is very time and energy inefficient. In this paper, we propose a coprocessor for accelerating the training of Convolutional Neural Network using a Xilinx Kintex Ultrascale XCKU085 based HTG-K800 FPGA board. DCNN is trained using back propagation algorithm. The coprocessor can be configured for a new network structure by changing the contents of Block Memory in the FPGA, without re-synthesizing and implementing using the design software. The reconfigurability through DDR can be supported with the architecture but is not implemented. The implementation achieves a maximum throughput of 280GOp/s.