FPGA Implementation of High Speed and Low Power Viterbi Decoder Using Reverse Algorithm of Convolution Encoder

K. Ramesh; S. Sudha

doi:10.1166/jctn.2017.7042

ScienceGate Book Chapters

JOURNAL ARTICLE

FPGA Implementation of High Speed and Low Power Viterbi Decoder Using Reverse Algorithm of Convolution Encoder

K. Ramesh S. Sudha

Year: 2017 Journal: Journal of Computational and Theoretical Nanoscience Vol: 14 (12)Pages: 5957-5962 Publisher: American Scientific Publishers

DOI: 10.1166/jctn.2017.7042

Get Full-Text PDF Get Analytical Report

Keywords:

Viterbi decoder Computer science Field-programmable gate array Encoder Parallel computing Viterbi algorithm Soft output Viterbi algorithm Convolution (computer science) Algorithm Soft-decision decoder Power (physics) Convolutional code Computer hardware Decoding methods Sequential decoding Artificial intelligence Operating system

Metrics

Cited By

0.00

FWCI (Field Weighted Citation Impact)

Refs

0.23

Citation Normalized Percentile

Is in top 1%

Is in top 10%

Topics

Telecommunications and Broadcasting Technologies

Physical Sciences → Engineering → Media Technology

FPGA Implementation of High Speed and Low Power Viterbi Decoder Using Reverse Algorithm of Convolution Encoder

Metrics

Topics

Related Documents

Implementation of High Speed Viterbi Decoder using FPGA

Design and Implementation of High Speed Viterbi Decoder and Convolution Encoder for SDR

Efficient implementation of Convolution Encoder and Viterbi Decoder

Low Power VLSI Implementation of Convolution Encoder and Viterbi Decoder using Verilog HDL

FPGA Implementation of High Speed Convolutional Encoder and Viterbi Decoder for Software Defined Radio