Implementation of High Speed Viterbi Decoder using FPGA

Amruta J. Mandwale; Altaf O. Mulani

doi:10.17577/ijertv5is020074

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Implementation of High Speed Viterbi Decoder using FPGA

Amruta J. Mandwale Altaf O. Mulani

Year: 2016 Journal: International Journal of Engineering Research and Vol: V5 (02) Publisher: International Research Publication House

DOI: 10.17577/ijertv5is020074

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Keywords:

Viterbi decoder Field-programmable gate array Computer science Soft output Viterbi algorithm Soft-decision decoder Viterbi algorithm Parallel computing Computer hardware Decoding methods Algorithm Sequential decoding

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Telecommunications and Broadcasting Technologies

Physical Sciences → Engineering → Media Technology

Implementation of High Speed Viterbi Decoder using FPGA

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