A Low-Power Hybrid-Integrated 40-Gb/s Optical Receiver in Silicon

Abstract

A low-power hybrid-integrated 40-Gb/s optical receiver is reported. The receiver consists of a broadband photodiode fabricated in a 0.18-μm Ge-on-SOI process packaged with an mm-wave electronic chip fabricated in a 0.13-μm SiGe BiCMOS process. The electronic chip consists of a low-noise transimpedance amplifier front-end, a three-stage Cherry-Hooper limiting amplifier, an output driver, and an offset cancellation network. The effect of the bond-wires, as the interface between the photonic and electronic chips, on the overall performance of the receiver is studied. The sensitivity level remains better than -11.0 dBm (bit error rate ≤ 10-12) with bond-wire length variation from 300 to 600 μm enabling a low-cost and reliable packaging solution for such optical receivers. The measured eye diagram has a 100-mVpp single-ended opening at 40 Gb/s. The receiver consumes 77 mW.