A multi-path high speed Viterbi decoder

Abstract

In this work, a multi-path Trace-Back Viterbi decoder architecture is proposed. It offers almost ideal error correction quality with relatively low overhead. Moreover, a technique that enhances the error correction quality of Register-Exchange decoders as well as a normalization technique that saves considerable area are introduced. The proposed techniques can be utilized for efficient realizations of high speed systolic as well as low speed sequential Viterbi decoder architectures.