VLSI implementation of a high-speed and low-power punctured Viterbi decoder

Abstract

This paper presents a new architecture of punctured Viterbi decoder with high-speed and low-power based on the modified T-algorithm and trace-back method. To gain high throughput and short decoding latency, parallel computations in ACSU and SMU are adopted. Furthermore, to save the power consumption, the unnecessary computations of path metric are omitted in the add-compare-select-unit (ACSU) and the already generated back-tracing routes are reused to reduce the times of trace-back operations in the survivor-memory-unit (SMU). The decoding latency of the (2,1,7) Viterbi decoder is only 34 clock cycles, the total average power is 185 mW with 200 Mb/s throughput using 0.25 /spl mu/m CMOS technology.