Design and Implementation of Low Power High Speed Viterbi Decoder

Abstract

This paper describes the design of Viterbi decoding algorithm and presents an implementation of the decoder for the UWB MB_OFDM technology. The Viterbi algorithm is a maximum-likelihood algorithm for decoding of convolution codes. The algorithm tries to find a path of the trellis diagram, where the sequence of output symbols approximately matches the received sequence. To accomplish this task, it calculates for each path the path metric, which measures the distance to the received symbols sequence. BMU calculates the distance (metric) between the received noisy symbol and the output symbol of the state transition (branch). ACSU computes the accumulated metric associated with the sequence of transitions (path) to reach a state. When more then a path arrives to a state, ACSU selects the path with the lowest metric value, which is the survivor path. SMU stores the information that permits to trace back from a state to the previous one. This work also includes the design of ½ convolution encoder. The over all System will be designed using HDL language and simulation, synthesis and implementation (Translation, Mapping, Placing and Routing) will be done using various FPGA based EDA Tools. Finally the proposed system architecture performance speed, area, power and throughput.