Design and implementation of an efficient RSA crypto-processor

Abstract

The RSA algorithm is widely used for information security today. This paper improves the architecture of the modular multiplier and also presents a new RSA encryption and decryption strategy to diminish greatly the time cost for RSA crypto-system to deal with the long data. An efficient RSA crypto-processor is designed by combining the traditional and new strategies of encryption and decryption. The verification prototype of this processor is built on the FPGA. The speed to deal with the short data reaches 150kbit/s under 317.6 MHz clock frequency. When dealing with data of 100Mbits length, the encryption speed reaches 29Mb/s. The decryption speed reaches 14Mb/s on average.