Design and implementation of low power floating point arithmetic unit

Abstract

This paper proposes implementation of IEEE floating point (FP) multiplication, addition and subtraction. Arithmetic on IEEE FP numbers imposes more challenges compared to fixed-point arithmetic. These particularly include the simultaneous computation of normalization and rounding. We show the efficient way of solving these challenges for the implementation of floating point (FP) addition, subtraction and multiplication. The proposed designs aim at reducing power dissipation. Here multi threshold voltage technique is used for reducing power dissipation. The proposed implementations are according to the IEEE 754 FP standard.