Low Latency VLSI Architecture for the Radix-4 CORDIC Algorithm

Abstract

The current trend of hardware intensive signal processing is based on the CORDIC. Over the years many architectures have been proposed to address issues pertaining to throughput and latency. In this paper, we are proposing a pipelined architecture for the VLSI implementation of radix-4 CORDIC rotator with redundant arithmetic to achieve low latency compared to the available architectures.