Process development and optimization for high-aspect ratio through-silicon via (TSV) etch

Abstract

Etch is one of the most critical processes for high-aspect ratio TSV as it defines the profile and wafer level depth uniformity of TSV, thus having a great impact on other downstream processes in TSV module and TSV backside reveal. This paper presents the challenges encountered in developing the 6μm × 55μm TSV (6μm diameter × 55μm depth) with a number of continuous process optimizations. These include improvements to the notch below the hard-mask, an increase in the post-etch resist retention, within wafer depth uniformity and higher silicon etch rate improving the throughput. TSV scaling to 3μm × 50μm with a higher aspect ratio is also demonstrated. This paper also describes details for setup of an Automatic Process Controller (APC) for TSV depth control in a manufacturing environment.