Standard cell floorplanning within the FHDL automatic placement tool

Abstract

Techniques which are being developed for the floorplanning of layouts in the Florida Hardware Design Language (FHDL) layout tool are present. These techniques show a different approach to the floorplanning of those layouts which are to contain a mixture of standard cells and macrocells. General cell placement and floorplanning are discussed. Standard cell collection, block generation, and placement optimization are discussed.< >