Practical Automatic Placement for Standard-Cell Integrated Circuits

Abstract

SYNOPTIC ABSTRACTThis paper introduces the placement problem that arises in the established standard-cell-style design of integrated circuit (IC) parts, and reports on a method for effectively solving this problem. The placement problem is to assign geometric coordinates on the two-dimensional IC “chip” to its many small, predesigned logic functions (standard cells). Applying a practical, simulated-annealing search to the critical placement problem as part of designing an IC can have a surprisingly large impact on a part's cost and manufacturability.Results from a recent benchmarking contest illustrate the importance of effectively solving the placement problem, and support the effectiveness of the methods introduced in this paper. The new solution method applies simulated-annealing search using an approximate placement model (considering only bounding boxes of the logical nets, and considering only approximate, fixed-grid carrier locations for the cells that define the boxes), adaptive wiring congestion estimates in the search objective, and parallel searches from random starts. Simulated-annealing search is tuned to allocate most computer execution time to “considering” global optimizations to the placement. Sandia's Madhat computer code implements a search based on these techniques. We executed Madhat in parallel on several workstation computers to find the best placement entered in the contest.