An efficient metric normalization architecture for high-speed low-power viterbi decoder

Abstract

In this paper, a new efficient metric normali zation architecture called High Bit Clear is proposed for a high throughput and low power Viterbi Decoder (VD). The proposed High Bit Clear normalization circuit not only normalizes all of the survivor path metrics, but also operates as close as the Add-Compare-Select (ACS) iteration bound possibly with a small area overhead. After we verified the function and made the platform by FPGA, we also used United Microelectronics Corporation (UMC) 0.18μm 1.8V 1P6M Standard Cell Library to implement it.