High speed low power architecture for memory management in a Viterbi decoder

Abstract

The management of the surviving-path memory in the Viterbi algorithm is generally performed by Trace-Back or Exchange Register. It has been shown that combining these two techniques leads to efficient realisation. In the present work, formal expressions of computational power, memory and latency are presented for several classes of algorithms. For v=4, L=64 Viterbi decoder, this formalism helps to find two algorithms that respectively reduce by a factor of 4 and 7 respectively, the computational power compared to a direct Exchange Register. Implementation results-place&route netlist generated through VHDL synthesis-and theoretical results are in concordance.