Abstract

The counting oy the consecutive ionization clusters in a drift chamber is a very promising technique for particle identification purposes. Up to noy the bottleneck for the application of this technique wat the possibility of realizing a large number of very-fast read-out channels with reduce power consumption. Typical time separation between each ionization act in a helium-based gas mixture is from a few ns to a few tens of ns. Thu. The read-out interface has to be able to process such a high-speed signals. In this paper. The first realization of a CMOS 0.13μm integrated readout circuit, including a fast variable gain amplifier (VGA) with 160MHz bandwidth is designed for the central tracker of a future collider (ILC, superB). The VGA circuit has been optimized for low power consumption. Moreover, it presents a programmable power consumption (8.4 mA, 9.4mA, 10.6mA) according to the gain setting (0dB, 10dB, 20dB). The design issues an. The measured performance associated to this architecture are discussed. © 2009 IEEE.

Keywords:
Video Graphics Array CMOS Bottleneck Bandwidth (computing) Physics Amplifier Computer science Electrical engineering Electronic engineering Optoelectronics Engineering Embedded system Telecommunications

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Topics

Particle Detector Development and Performance
Physical Sciences →  Physics and Astronomy →  Nuclear and High Energy Physics
CCD and CMOS Imaging Sensors
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Analog and Mixed-Signal Circuit Design
Physical Sciences →  Engineering →  Biomedical Engineering
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