JOURNAL ARTICLE

1–10GHz inductorless receiver in 0.13µm CMOS

Abstract

In this paper, we describe an inductorless wideband radio receiver architecture from 1 GHz to 10 GHz. Two receiver RF frontends designs are presented and compared: a traditional inductor peaking LNA and mixer (IPLM) and a capacitive peaking LNA and mixer circuit (CPLM). Measurement results indicate that CPLM with the same bandwidth has better linearity, comparable noise figure and uses only 17% more power. The silicon area for the CPLM is only 22% of the IPLM. Both designs can be mated with an inductorless, ring-oscillator based, wide lock range and low power PLL also shown in this paper.

Keywords:
CMOS Wideband Linearity Phase-locked loop Electrical engineering Bandwidth (computing) Inductor Noise figure Electronic engineering Capacitive sensing Phase noise Computer science Physics Engineering Telecommunications Voltage Amplifier

Metrics

6
Cited By
1.06
FWCI (Field Weighted Citation Impact)
13
Refs
0.82
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Radio Frequency Integrated Circuit Design
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Advancements in PLL and VCO Technologies
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Microwave Engineering and Waveguides
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
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