A Two-level Hybrid Select Logic for Wide-Issue Superscalar Processors

Abstract

In a superscalar processor, select logic within the critical path of the instruction queue has become a performance bottleneck. This paper presents a high speed, two-level, hybrid select logic for wide-issue processors. The first level reduces delay by performing parallel age-based selection, and final arbitration is achieved in the second level with simple position-based select logic. The hybrid select logic circuits were implemented in dynamic logic on IBM 0.13/spl mu/m technology. Simulation shows 36% reduction in delay with less than 1% IPC degradation compared to the conventional design.