Simplifying instruction issue logic in superscalar processors

Abstract

Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instruction scheduling capability. However, it is difficult to increase the size without any serious impact on processor performance, since the instruction window is one of the dominant determiners of processor cycle time. The instruction window is critical because it is realized using content addressable memory (CAM). In general, RAMs are faster in access time and lower in power dissipation than CAMs. Therefore, it is desirable that the CAM instruction window is replaced by the RAM instruction window. This paper proposes such an instruction window, named the explicit data forwarding instruction window. The principle behind our proposal is to make result forwarding explicit. It is possible to dynamically construct explicit relationships between instructions, since it is expected that each execution result is forwarded to a limited number of dependent instructions. Simulation results show that the explicit data forwarding instruction window achieves a level of performance comparable to that of the conventional instruction window, while also providing benefit in terms of shorter cycle time.