30-nm two-step recess gate InP-Based InAlAs/InGaAs HEMTs

Abstract

The two-step recess gate technology has been developed for sub-100-nm gate InP-based InAlAs/InGaAs high-electron mobility transistors (HEMTs). This gate structure is found to be advantageous for the preciseness of the metallurgical gate length as well as a comparable stability to the conventional gate structure with an InP etch stop layer. The two-step recess gate is optimized focusing on the lateral width of the gate recess. Due to the stability of the gate recess with InP surface, a laterally wide gate recess gives the maximum cutoff frequency, lower gate leakage current, smaller output conductance and higher maximum frequency of oscillation. Finally, the uniformity of the device characteristics evaluated for sub-100-nm HEMTs with the optimized recess width. The result reveals the significant role of the short channel effects on the device uniformity.