Low-voltage analog CMOS filter design

Abstract

Design techniques for low-voltage analog filters in CMOS technologies are discussed. The use of operational transconductance amplifier (OTA)-C implementation techniques toward low power supply voltages (3 V and below) requires special source degeneration and input signal folding techniques. Design techniques to achieve full CMOS continuous-time filters with low distortion (total harmonic distortion < -50 dB) and low power supply voltages (3 V) are discussed. The use of switched-capacitor techniques at extremely low voltages (1.5 V) requires extra care for the switches in the circuit. Special design techniques, such as voltage multipliers for the clock drivers and single transistor switches, are analyzed to achieve the low power supply specifications.< >