A 0.65V, 2.4GHz CMOS low-noise amplifiers design with noise optimization

Muneer Khan; Yanjie Wang; Sara Ali; R. Raut

doi:10.1109/ccece.2005.1557020

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A 0.65V, 2.4GHz CMOS low-noise amplifiers design with noise optimization

Muneer Khan Yanjie Wang Sara Ali R. Raut

Year: 2005 Pages: 673-676

DOI: 10.1109/ccece.2005.1557020

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Abstract

A 0.65 V, 2.4 GHz low noise amplifier (LNA) has been designed and simulated using spectre simulator in a standard TSMC 0.18 mum CMOS technology. With low power and noise optimization techniques, the amplifier provides a gain of 27 dB, a noise figure of only 1.1 dB, power dissipation of 4.6 mW from a 0.65 V power supply

Keywords:

Low-noise amplifier CMOS Effective input noise temperature Noise figure Amplifier Noise (video) Electrical engineering Noise temperature Noise-figure meter Electronic engineering Y-factor Amplifier figures of merit Noise measurement Computer science Noise generator Engineering Physics Phase noise Acoustics Noise reduction

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Radio Frequency Integrated Circuit Design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Analog and Mixed-Signal Circuit Design

Physical Sciences → Engineering → Biomedical Engineering

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Physical Sciences → Engineering → Electrical and Electronic Engineering

A 0.65V, 2.4GHz CMOS low-noise amplifiers design with noise optimization

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