Silicon masking layers for fabrication of high aspect ratio MEMS

Abstract

This paper presents a fabrication technique for high-aspect ratio MEMS using a planar silicon layer bonded to a structured substrate. The bonded silicon layer provides a flat surface that can be patterned by conventional photolithography. These patterns are then transferred to the substrate through a series of etch steps. The bonded silicon layer is etched together with the substrate, so the use of additional silicon masking layers, followed by patterning and etching, can be repeated as many times as necessary. Using this approach, we have successfully demonstrated vertical mirror fabrication by a combination of KOH and DRIE etching in (110) silicon