Hole mobility enhancement in strained-Si/strained-SiGe heterostructure p-MOSFETs fabricated on SiGe-on-insulator (SGOI)

Abstract

Dual-channel heterostructures, with a tensile strained-Si layer (for electron channel) and a compressively strained-Si0.4Ge0.6 layer (for hole channel) on relaxed-Si0.7Ge0.3-on-insulator (SGOI) substrates were fabricated by bond, etch-back and epitaxial regrowth. Partially depleted p-MOSFETs were made on this strained-Si/strained-SiGe SGOI heterostructure. The hole mobility shows an enhancement of about 1.8 times at 0.2 MV cm−1, equivalent to that obtained on co-processed strained-Si/strained-SiGe p-MOSFETs fabricated on bulk relaxed Si0.7Ge0.3 virtual substrates. The limited thermal budget issue for this heterostructure is also discussed.