A VLSI array CORDIC architecture

Abstract

Use of the CORDIC (COordinate Rotation DIgital Computer) algorithm has been proposed for signal processing applications, since it has been shown that many DSP algorithms are fundamentally described by generalized rotations. However, the iterative nature of CORDIC has diminished its utility in high-speed real-time signal processing applications. The authors propose an array architecture for VLSI implementation of the CORDIC algorithm that aims to circumvent this shortcoming. The size and speed of the structure is compared with those of array multiplier and array divider structures. It is shown that the array CORDIC, while consuming a larger absolute real estate than these other structures, provides a better speed/area tradeoff as well as a rich set of elementary functions.< >