Algorithms and architectures for concurrent Viterbi decoding

Abstract

The sequential nature of the Vitterbi algorithm places an inherent upper limit on the decoding throughput of the algorithm in a given integrated circuit technology and thereby restricts its applications. Three methods of generating inherently unlimited concurrency in Viterbi decoding, for both controllable and uncontrollable shift register processes and Markov processes, are described. Concurrent decoders using these methods can apply high-throughput architectures with an overhead of pipeline latches or parallel hardware. A feasible method for bypassing the hardware limit is also proposed for decoding at an arbitrarily high as well as variable throughput. The proposed methods make real-time Viterbi decoding in the gigabit-per-second range feasible for convolutional and trellis codes.< >