A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm

Abstract

In this paper we describe the implementation of a K = 7, R = 1/2 single-chip Viterbi decoder intended to operate at 10-20 Mbit/sec. We propose a general, regular and area efficient floor-plan that is also suitable for implementation of decoders for codes with different generator polynomials or different values of K. The Shuffle-Exchange type interconnection network is implemented by organizing the 64 processing elements to form a ring. The ring is laid out in two columns, and the interconnections between non-neighbours are routed in the channel between the columns. The interconnection network occupies 32% of the area, and the global signals (including power) occupy a further 10%. A test-chip containing a pair of processing elements has been fabricated via NORCHIP (the Scandinavian CMOS IC prototype implementation service). This chip has been fully tested, and it operates correctly at speeds above 26 MHz under worst-case conditions (V _DD = 4.75 V and T _A = 70°C).